Synopsys Debuts the HAPS-200 and the ZeBu-200
References: prnewswire
Synopsys has introduced its latest hardware-assisted verification systems — the HAPS-200 and ZeBu-200. These innovations are designed to address the growing complexity of semiconductor designs.
The hardware-assisted verification systems are built on the new EP-Ready Hardware platform. Synopsys claims its innovation offers significant advancements in performance, scalability, and flexibility in order to cater to the needs of next-generation chip development. The HAPS-200 prototyping system boasts a 2X performance improvement over its predecessor, along with faster compile times and enhanced debug capabilities. It supports scalability from single FPGA setups to multi-rack configurations. Similarly, the ZeBu-200 emulation system delivers double the runtime performance and improved debug bandwidth, making it suitable for large-scale designs of up to 15.4 billion gates.
With the semiconductor industry pushing toward designs with hundreds of billions of gates and millions of lines of software code, Synopsys’ solutions aim to streamline verification processes, reduce development time, and enhance productivity for engineers working on advanced system-on-chip and multi-die architectures.
Image Credit: Synopsys
The hardware-assisted verification systems are built on the new EP-Ready Hardware platform. Synopsys claims its innovation offers significant advancements in performance, scalability, and flexibility in order to cater to the needs of next-generation chip development. The HAPS-200 prototyping system boasts a 2X performance improvement over its predecessor, along with faster compile times and enhanced debug capabilities. It supports scalability from single FPGA setups to multi-rack configurations. Similarly, the ZeBu-200 emulation system delivers double the runtime performance and improved debug bandwidth, making it suitable for large-scale designs of up to 15.4 billion gates.
With the semiconductor industry pushing toward designs with hundreds of billions of gates and millions of lines of software code, Synopsys’ solutions aim to streamline verification processes, reduce development time, and enhance productivity for engineers working on advanced system-on-chip and multi-die architectures.
Image Credit: Synopsys
Trend Themes
1. Hardware-accelerated Verification - Leveraging hardware-accelerated systems like HAPS-200 and ZeBu-200 can drastically reduce verification times and accommodate the demands of complex semiconductor designs.
2. Scalable Prototyping Solutions - The adoption of scalable prototyping systems enables efficient transitions from single FPGA setups to expansive multi-rack configurations, addressing diverse design needs.
3. Next-generation Chip Development - Focusing on systems that enhance performance, scalability, and flexibility can drive progress in developing advanced system-on-chip and multi-die architectures.
Industry Implications
1. Semiconductor Manufacturing - Innovative verification systems like those introduced by Synopsys could reshape semiconductor manufacturing by streamlining the development of increasingly complex designs.
2. Electronic Design Automation - Electronic design automation industry stands to benefit from advancements in hardware-assisted verification tools, significantly enhancing engineers' productivity and design accuracy.
3. Computing Hardware - Incorporating advanced verification systems into computing hardware development can facilitate the creation of devices capable of handling the next generation of computing demands.
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